Documentation/devicetree/bindings/clock/imx7ulp-pcc-clock.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/clock/imx7ulp-pcc-clock.yaml

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System
Linux kernel
Corpus path
Documentation/devicetree/bindings/clock/imx7ulp-pcc-clock.yaml
Extension
.yaml
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3422 bytes
Lines
111
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX7ULP Peripheral Clock Control (PCC) modules Clock Controller

maintainers:
  - A.s. Dong <aisheng.dong@nxp.com>

description: |
  i.MX7ULP Clock functions are under joint control of the System
  Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
  modules, and Core Mode Controller (CMC)1 blocks

  The clocking scheme provides clear separation between M4 domain
  and A7 domain. Except for a few clock sources shared between two
  domains, such as the System Oscillator clock, the Slow IRC (SIRC),
  and and the Fast IRC clock (FIRCLK), clock sources and clock
  management are separated and contained within each domain.

  M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
  A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.

  Note: this binding doc is only for A7 clock domain.

  The Peripheral Clock Control (PCC) is responsible for clock selection,
  optional division and clock gating mode for peripherals in their
  respected power domain.

  The clock consumer should specify the desired clock by having the clock
  ID in its "clocks" phandle cell.
  See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
  i.MX7ULP clock IDs of each module.

properties:
  compatible:
    enum:
      - fsl,imx7ulp-pcc2
      - fsl,imx7ulp-pcc3

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

  clocks:
    items:
      - description: nic1 bus clock
      - description: nic1 clock
      - description: ddr clock
      - description: apll pfd2
      - description: apll pfd1
      - description: apll pfd0
      - description: usb pll
      - description: system osc bus clock
      - description: fast internal reference clock bus
      - description: rtc osc
      - description: system pll bus clock

  clock-names:
    items:
      - const: nic1_bus_clk
      - const: nic1_clk
      - const: ddr_clk
      - const: apll_pfd2
      - const: apll_pfd1
      - const: apll_pfd0

Annotation

Implementation Notes