Documentation/devicetree/bindings/clock/keystone-pll.txt

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/clock/keystone-pll.txt

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Linux kernel
Corpus path
Documentation/devicetree/bindings/clock/keystone-pll.txt
Extension
.txt
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2632 bytes
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83
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: documentation
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Detected Declarations

Annotated Snippet

Binding for keystone PLLs. The main PLL IP typically has a multiplier,
a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
and PAPLL are controlled by the memory mapped register where as the Main
PLL is controlled by a PLL controller registers along with memory mapped
registers.

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- #clock-cells : from common clock binding; shall be set to 0.
- compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
- clocks : parent clock phandle
- reg - pll control0 and pll multiplier registers
- reg-names : control, multiplier and post-divider. The multiplier and
		post-divider registers are applicable only for main pll clock
- fixed-postdiv : fixed post divider value. If absent, use clkod register bits
		for postdiv

Example:
	mainpllclk: mainpllclk@2310110 {
		#clock-cells = <0>;
		compatible = "ti,keystone,main-pll-clock";
		clocks = <&refclksys>;
		reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
		reg-names = "control", "multiplier", "post-divider";
		fixed-postdiv = <2>;
	};

	papllclk: papllclk@2620358 {
		#clock-cells = <0>;
		compatible = "ti,keystone,pll-clock";
		clocks = <&refclkpass>;
		clock-output-names = "pa-pll-clk";
		reg = <0x02620358 4>;
		reg-names = "control";
	};

Required properties:
- #clock-cells : from common clock binding; shall be set to 0.
- compatible : shall be "ti,keystone,pll-mux-clock"
- clocks : link phandles of parent clocks
- reg - pll mux register
- bit-shift : number of bits to shift the bit-mask
- bit-mask : arbitrary bitmask for programming the mux

Optional properties:
- clock-output-names : From common clock binding.

Example:
	mainmuxclk: mainmuxclk@2310108 {
		#clock-cells = <0>;
		compatible = "ti,keystone,pll-mux-clock";
		clocks = <&mainpllclk>, <&refclkmain>;
		reg = <0x02310108 4>;
		bit-shift = <23>;
		bit-mask = <1>;
		clock-output-names = "mainmuxclk";
	};

Required properties:
- #clock-cells : from common clock binding; shall be set to 0.
- compatible : shall be "ti,keystone,pll-divider-clock"
- clocks : parent clock phandle
- reg - pll mux register
- bit-shift : number of bits to shift the bit-mask
- bit-mask : arbitrary bitmask for programming the divider

Optional properties:

Annotation

Implementation Notes