Documentation/devicetree/bindings/clock/mediatek,mt8195-clock.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/clock/mediatek,mt8195-clock.yaml

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System
Linux kernel
Corpus path
Documentation/devicetree/bindings/clock/mediatek,mt8195-clock.yaml
Extension
.yaml
Size
6127 bytes
Lines
239
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt8195-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek Functional Clock Controller for MT8195

maintainers:
  - Chun-Jie Chen <chun-jie.chen@mediatek.com>

description:
  The clock architecture in Mediatek like below
  PLLs -->
          dividers -->
                      muxes
                           -->
                              clock gate

  The devices except apusys_pll provide clock gate control in different IP blocks.
  The apusys_pll provides Plls which generated from SoC 26m for AI Processing Unit.

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt8195-scp_adsp
          - mediatek,mt8195-imp_iic_wrap_s
          - mediatek,mt8195-imp_iic_wrap_w
          - mediatek,mt8195-mfgcfg
          - mediatek,mt8195-wpesys
          - mediatek,mt8195-wpesys_vpp0
          - mediatek,mt8195-wpesys_vpp1
          - mediatek,mt8195-imgsys
          - mediatek,mt8195-imgsys1_dip_top
          - mediatek,mt8195-imgsys1_dip_nr
          - mediatek,mt8195-imgsys1_wpe
          - mediatek,mt8195-ipesys
          - mediatek,mt8195-camsys
          - mediatek,mt8195-camsys_rawa
          - mediatek,mt8195-camsys_yuva
          - mediatek,mt8195-camsys_rawb
          - mediatek,mt8195-camsys_yuvb
          - mediatek,mt8195-camsys_mraw
          - mediatek,mt8195-ccusys
          - mediatek,mt8195-vdecsys_soc
          - mediatek,mt8195-vdecsys
          - mediatek,mt8195-vdecsys_core1
          - mediatek,mt8195-vencsys
          - mediatek,mt8195-vencsys_core1
          - mediatek,mt8195-apusys_pll
  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    scp_adsp: clock-controller@10720000 {
        compatible = "mediatek,mt8195-scp_adsp";
        reg = <0x10720000 0x1000>;
        #clock-cells = <1>;
    };

Annotation

Implementation Notes