Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml
Extension
.yaml
Size
3937 bytes
Lines
113
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt8196-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek Functional Clock Controller for MT8196

maintainers:
  - Guangjie Song <guangjie.song@mediatek.com>
  - Laura Nao <laura.nao@collabora.com>

description: |
  The clock architecture in MediaTek SoCs is structured like below:
  PLLs -->
          dividers -->
                      muxes
                           -->
                              clock gate

  The device nodes provide clock gate control in different IP blocks.

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt8196-imp-iic-wrap-c
          - mediatek,mt8196-imp-iic-wrap-e
          - mediatek,mt8196-imp-iic-wrap-n
          - mediatek,mt8196-imp-iic-wrap-w
          - mediatek,mt8196-mdpsys0
          - mediatek,mt8196-mdpsys1
          - mediatek,mt8196-pericfg-ao
          - mediatek,mt8196-pextp0cfg-ao
          - mediatek,mt8196-pextp1cfg-ao
          - mediatek,mt8196-ufscfg-ao
          - mediatek,mt8196-vencsys
          - mediatek,mt8196-vencsys-c1
          - mediatek,mt8196-vencsys-c2
          - mediatek,mt8196-vdecsys
          - mediatek,mt8196-vdecsys-soc
          - mediatek,mt8196-vdisp-ao
      - const: syscon

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1
    description:
      Reset lines for PEXTP0/1 and UFS blocks.

  mediatek,hardware-voter:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: |
      Phandle to the "Hardware Voter" (HWV), as named in the vendor
      documentation for MT8196/MT6991.

      The HWV is a SoC-internal fixed-function MCU used to collect votes from
      both the Application Processor and other remote processors within the SoC.
      It is intended to transparently enable or disable hardware resources (such
      as power domains or clocks) based on internal vote aggregation handled by
      the MCU's internal state machine.

      However, in practice, this design is incomplete. While the HWV performs
      some internal vote aggregation,software is still required to
      - Manually enable power supplies externally, if present and if required

Annotation

Implementation Notes