Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml

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Linux kernel
Corpus path
Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml
Extension
.yaml
Size
3942 bytes
Lines
108
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt8196-sys-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek System Clock Controller for MT8196

maintainers:
  - Guangjie Song <guangjie.song@mediatek.com>
  - Laura Nao <laura.nao@collabora.com>

description: |
  The clock architecture in MediaTek SoCs is structured like below:
  PLLs -->
          dividers -->
                      muxes
                           -->
                              clock gate

  The apmixedsys, apmixedsys_gp2, vlpckgen, armpll, ccipll, mfgpll and ptppll
  provide most of the PLLs which are generated from the SoC's 26MHZ crystal oscillator.
  The topckgen, topckgen_gp2 and vlpckgen provide dividers and muxes which
  provide the clock source to other IP blocks.

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt8196-apmixedsys
          - mediatek,mt8196-armpll-b-pll-ctrl
          - mediatek,mt8196-armpll-bl-pll-ctrl
          - mediatek,mt8196-armpll-ll-pll-ctrl
          - mediatek,mt8196-apmixedsys-gp2
          - mediatek,mt8196-ccipll-pll-ctrl
          - mediatek,mt8196-mfgpll-pll-ctrl
          - mediatek,mt8196-mfgpll-sc0-pll-ctrl
          - mediatek,mt8196-mfgpll-sc1-pll-ctrl
          - mediatek,mt8196-ptppll-pll-ctrl
          - mediatek,mt8196-topckgen
          - mediatek,mt8196-topckgen-gp2
          - mediatek,mt8196-vlpckgen
      - const: syscon

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

  mediatek,hardware-voter:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: |
      Phandle to the "Hardware Voter" (HWV), as named in the vendor
      documentation for MT8196/MT6991.

      The HWV is a SoC-internal fixed-function MCU used to collect votes from
      both the Application Processor and other remote processors within the SoC.
      It is intended to transparently enable or disable hardware resources (such
      as power domains or clocks) based on internal vote aggregation handled by
      the MCU's internal state machine.

      However, in practice, this design is incomplete. While the HWV performs
      some internal vote aggregation,software is still required to
      - Manually enable power supplies externally, if present and if required
      - Manually enable parent clocks via direct MMIO writes to clock controllers
      - Enable the FENC after the clock has been ungated via direct MMIO
      writes to clock controllers

      As such, the HWV behaves more like a hardware-managed clock reference

Annotation

Implementation Notes