Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml

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System
Linux kernel
Corpus path
Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml
Extension
.yaml
Size
8417 bytes
Lines
291
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/nvidia,tegra124-dfll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra124 (and later) DFLL FCPU clocksource

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

description:
  The DFLL IP block on Tegra is a root clocksource designed for clocking
  the fast CPU cluster. It consists of a free-running voltage controlled
  oscillator connected to the CPU voltage rail (VDD_CPU), and a closed
  loop control module that will automatically adjust the VDD_CPU voltage
  by communicating with an off-chip PMIC either via an I2C bus or via
  PWM signals.

properties:
  compatible:
    enum:
      - nvidia,tegra124-dfll
      - nvidia,tegra210-dfll

  reg:
    items:
      - description: DFLL control logic
      - description: I2C output logic
      - description: Integrated I2C controller
      - description: Look-up table RAM for voltage register values

  interrupts:
    maxItems: 1

  "#clock-cells":
    const: 0

  clocks:
    items:
      - description: Clock source for the DFLL control logic
      - description: Closed loop reference clock
      - description: Clock source for the integrated I2C controller

  clock-names:
    items:
      - const: soc
      - const: ref
      - const: i2c

  clock-output-names:
    description: Name of the clock output
    items:
      - const: dfllCPU_out

  resets:
    minItems: 1
    maxItems: 2

  reset-names:
    minItems: 1
    items:
      - const: dvco
      - const: dfll

  vdd-cpu-supply:
    description: Regulator for the CPU voltage rail that the DFLL
      hardware will start controlling. The regulator will be queried for
      the I2C register, control values and supported voltages.

Annotation

Implementation Notes