Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml- Extension
.yaml- Size
- 2759 bytes
- Lines
- 107
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/clock/qcom,rpmcc.hdt-bindings/clock/qcom,gcc-sm6125.hdt-bindings/power/qcom-rpmpd.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock Controller on SM6125
maintainers:
- Martin Botka <martin.botka@somainline.org>
description: |
Qualcomm display clock control module provides the clocks and power domains
on SM6125.
See also: include/dt-bindings/clock/qcom,dispcc-sm6125.h
properties:
compatible:
enum:
- qcom,sm6125-dispcc
clocks:
items:
- description: Board XO source
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
- description: Pixel clock from DSI PHY1
- description: Link clock from DP PHY
- description: VCO DIV clock from DP PHY
- description: AHB config clock from GCC
- description: GPLL0 div source from GCC
clock-names:
items:
- const: bi_tcxo
- const: dsi0_phy_pll_out_byteclk
- const: dsi0_phy_pll_out_dsiclk
- const: dsi1_phy_pll_out_dsiclk
- const: dp_phy_pll_link_clk
- const: dp_phy_pll_vco_div_clk
- const: cfg_ahb_clk
- const: gcc_disp_gpll0_div_clk_src
'#clock-cells':
const: 1
'#power-domain-cells':
const: 1
power-domains:
description:
A phandle and PM domain specifier for the CX power domain.
maxItems: 1
required-opps:
description:
A phandle to an OPP node describing the power domain's performance point.
maxItems: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#power-domain-cells'
Annotation
- Immediate include surface: `dt-bindings/clock/qcom,rpmcc.h`, `dt-bindings/clock/qcom,gcc-sm6125.h`, `dt-bindings/power/qcom-rpmpd.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.