Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml

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System
Linux kernel
Corpus path
Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml
Extension
.yaml
Size
1971 bytes
Lines
75
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6350.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display Clock & Reset Controller on SM6350

maintainers:
  - Konrad Dybcio <konradybcio@kernel.org>

description: |
  Qualcomm display clock control module provides the clocks, resets and power
  domains on SM6350.

  See also: include/dt-bindings/clock/qcom,dispcc-sm6350.h

properties:
  compatible:
    const: qcom,sm6350-dispcc

  clocks:
    items:
      - description: Board XO source
      - description: GPLL0 source from GCC
      - description: Byte clock from DSI PHY
      - description: Pixel clock from DSI PHY
      - description: Link clock from DP PHY
      - description: VCO DIV clock from DP PHY

  clock-names:
    items:
      - const: bi_tcxo
      - const: gcc_disp_gpll0_clk
      - const: dsi0_phy_pll_out_byteclk
      - const: dsi0_phy_pll_out_dsiclk
      - const: dp_phy_pll_link_clk
      - const: dp_phy_pll_vco_div_clk

required:
  - compatible
  - clocks
  - clock-names
  - '#power-domain-cells'

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sm6350.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@af00000 {
      compatible = "qcom,sm6350-dispcc";
      reg = <0x0af00000 0x20000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&gcc GCC_DISP_GPLL0_CLK>,
               <&dsi_phy 0>,
               <&dsi_phy 1>,
               <&dp_phy 0>,
               <&dp_phy 1>;
      clock-names = "bi_tcxo",
                    "gcc_disp_gpll0_clk",
                    "dsi0_phy_pll_out_byteclk",
                    "dsi0_phy_pll_out_dsiclk",
                    "dp_phy_pll_link_clk",
                    "dp_phy_pll_vco_div_clk";
      #clock-cells = <1>;

Annotation

Implementation Notes