Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
Extension
.yaml
Size
3468 bytes
Lines
124
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display Clock & Reset Controller on SM8150/SM8250/SM8350

maintainers:
  - Jonathan Marek <jonathan@marek.ca>

description: |
  Qualcomm display clock control module provides the clocks, resets and power
  domains on SM8150/SM8250/SM8350.

  See also::
    include/dt-bindings/clock/qcom,dispcc-sm8150.h
    include/dt-bindings/clock/qcom,dispcc-sm8250.h
    include/dt-bindings/clock/qcom,dispcc-sm8350.h

properties:
  compatible:
    enum:
      - qcom,sc8180x-dispcc
      - qcom,sm8150-dispcc
      - qcom,sm8250-dispcc
      - qcom,sm8350-dispcc

  clocks:
    minItems: 7
    items:
      - description: Board XO source
      - description: Byte clock from DSI PHY0
      - description: Pixel clock from DSI PHY0
      - description: Byte clock from DSI PHY1
      - description: Pixel clock from DSI PHY1
      - description: Link clock from DP PHY
      - description: VCO DIV clock from DP PHY
      - description: Link clock from eDP PHY
      - description: VCO DIV clock from eDP PHY
      - description: Link clock from DP1 PHY
      - description: VCO DIV clock from DP1 PHY
      - description: Link clock from DP2 PHY
      - description: VCO DIV clock from DP2 PHY

  clock-names:
    minItems: 7
    items:
      - const: bi_tcxo
      - const: dsi0_phy_pll_out_byteclk
      - const: dsi0_phy_pll_out_dsiclk
      - const: dsi1_phy_pll_out_byteclk
      - const: dsi1_phy_pll_out_dsiclk
      - const: dp_phy_pll_link_clk
      - const: dp_phy_pll_vco_div_clk
      - const: edp_phy_pll_link_clk
      - const: edp_phy_pll_vco_div_clk
      - const: dptx1_phy_pll_link_clk
      - const: dptx1_phy_pll_vco_div_clk
      - const: dptx2_phy_pll_link_clk
      - const: dptx2_phy_pll_vco_div_clk

  power-domains:
    description:
      A phandle and PM domain specifier for the MMCX power domain.
    maxItems: 1

  required-opps:
    description:
      A phandle to an OPP node describing required MMCX performance point.

Annotation

Implementation Notes