Documentation/devicetree/bindings/clock/qcom,eliza-dispcc.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/clock/qcom,eliza-dispcc.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/clock/qcom,eliza-dispcc.yaml- Extension
.yaml- Size
- 2786 bytes
- Lines
- 97
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/clock/qcom,dsi-phy-28nm.hdt-bindings/clock/qcom,eliza-gcc.hdt-bindings/clock/qcom,rpmh.hdt-bindings/power/qcom,rpmhpd.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,eliza-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Display Clock & Reset Controller for Qualcomm Eliza SoC
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Konrad Dybcio <konradybcio@kernel.org>
- Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
description: |
Display clock control module provides the clocks, resets and power
domains on Qualcomm Eliza SoC platform.
See also:
- include/dt-bindings/clock/qcom,eliza-dispcc.h
properties:
compatible:
enum:
- qcom,eliza-dispcc
clocks:
items:
- description: Board XO source
- description: Board Always On XO source
- description: Display's AHB clock
- description: sleep clock
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
- description: Byte clock from DSI PHY1
- description: Pixel clock from DSI PHY1
- description: Link clock from DP PHY0
- description: VCO DIV clock from DP PHY0
- description: Link clock from DP PHY1
- description: VCO DIV clock from DP PHY1
- description: Link clock from DP PHY2
- description: VCO DIV clock from DP PHY2
- description: Link clock from DP PHY3
- description: VCO DIV clock from DP PHY3
- description: HDMI link clock from HDMI PHY
power-domains:
maxItems: 1
required-opps:
maxItems: 1
required:
- compatible
- clocks
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,eliza-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@af00000 {
compatible = "qcom,eliza-dispcc";
reg = <0x0af00000 0x20000>;
Annotation
- Immediate include surface: `dt-bindings/clock/qcom,dsi-phy-28nm.h`, `dt-bindings/clock/qcom,eliza-gcc.h`, `dt-bindings/clock/qcom,rpmh.h`, `dt-bindings/power/qcom,rpmhpd.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.