Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml
Extension
.yaml
Size
2866 bytes
Lines
99
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,glymur-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display Clock & Reset Controller on Glymur SoC

maintainers:
  - Taniya Das <taniya.das@oss.qualcomm.com>

description: |
  Qualcomm display clock control module which supports the clocks, resets and
  power domains for the MDSS instances on Glymur SoC.

  See also:
    include/dt-bindings/clock/qcom,dispcc-glymur.h

properties:
  compatible:
    enum:
      - qcom,glymur-dispcc

  clocks:
    items:
      - description: Board CXO clock
      - description: Board sleep clock
      - description: DisplayPort 0 link clock
      - description: DisplayPort 0 VCO div clock
      - description: DisplayPort 1 link clock
      - description: DisplayPort 1 VCO div clock
      - description: DisplayPort 2 link clock
      - description: DisplayPort 2 VCO div clock
      - description: DisplayPort 3 link clock
      - description: DisplayPort 3 VCO div clock
      - description: DSI 0 PLL byte clock
      - description: DSI 0 PLL DSI clock
      - description: DSI 1 PLL byte clock
      - description: DSI 1 PLL DSI clock
      - description: Standalone PHY 0 PLL link clock
      - description: Standalone PHY 0 VCO div clock
      - description: Standalone PHY 1 PLL link clock
      - description: Standalone PHY 1 VCO div clock

  power-domains:
    description:
      A phandle and PM domain specifier for the MMCX power domain.
    maxItems: 1

  required-opps:
    description:
      A phandle to an OPP node describing required MMCX performance point.
    maxItems: 1

required:
  - compatible
  - clocks
  - power-domains
  - '#power-domain-cells'

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/power/qcom,rpmhpd.h>

Annotation

Implementation Notes