Documentation/devicetree/bindings/clock/qcom,glymur-gcc.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/clock/qcom,glymur-gcc.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/clock/qcom,glymur-gcc.yaml
Extension
.yaml
Size
4634 bytes
Lines
122
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,glymur-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on Glymur SoC

maintainers:
  - Taniya Das <taniya.das@oss.qualcomm.com>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on Glymur SoC.

  See also: include/dt-bindings/clock/qcom,glymur-gcc.h

properties:
  compatible:
    const: qcom,glymur-gcc

  clocks:
    items:
      - description: Board XO source
      - description: Board XO_A source
      - description: Sleep clock source
      - description: USB 0 Phy DP0 GMUX clock source
      - description: USB 0 Phy DP1 GMUX clock source
      - description: USB 0 Phy PCIE PIPEGMUX clock source
      - description: USB 0 Phy PIPEGMUX clock source
      - description: USB 0 Phy SYS PCIE PIPEGMUX clock source
      - description: USB 1 Phy DP0 GMUX 2 clock source
      - description: USB 1 Phy DP1 GMUX 2 clock source
      - description: USB 1 Phy PCIE PIPEGMUX clock source
      - description: USB 1 Phy PIPEGMUX clock source
      - description: USB 1 Phy SYS PCIE PIPEGMUX clock source
      - description: USB 2 Phy DP0 GMUX 2 clock source
      - description: USB 2 Phy DP1 GMUX 2 clock source
      - description: USB 2 Phy PCIE PIPEGMUX clock source
      - description: USB 2 Phy PIPEGMUX clock source
      - description: USB 2 Phy SYS PCIE PIPEGMUX clock source
      - description: PCIe 3a pipe clock
      - description: PCIe 3b pipe clock
      - description: PCIe 4 pipe clock
      - description: PCIe 5 pipe clock
      - description: PCIe 6 pipe clock
      - description: QUSB4 0 PHY RX 0 clock source
      - description: QUSB4 0 PHY RX 1 clock source
      - description: QUSB4 1 PHY RX 0 clock source
      - description: QUSB4 1 PHY RX 1 clock source
      - description: QUSB4 2 PHY RX 0 clock source
      - description: QUSB4 2 PHY RX 1 clock source
      - description: UFS PHY RX Symbol 0 clock source
      - description: UFS PHY RX Symbol 1 clock source
      - description: UFS PHY TX Symbol 0 clock source
      - description: USB3 PHY 0 pipe clock source
      - description: USB3 PHY 1 pipe clock source
      - description: USB3 PHY 2 pipe clock source
      - description: USB3 UNI PHY pipe 0 clock source
      - description: USB3 UNI PHY pipe 1 clock source
      - description: USB4 PHY 0 pcie pipe clock source
      - description: USB4 PHY 0 Max pipe clock source
      - description: USB4 PHY 1 pcie pipe clock source
      - description: USB4 PHY 1 Max pipe clock source
      - description: USB4 PHY 2 pcie pipe clock source
      - description: USB4 PHY 2 Max pipe clock source

required:
  - compatible
  - clocks

Annotation

Implementation Notes