Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml
Extension
.yaml
Size
4934 bytes
Lines
138
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,x1e80100-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on X1E80100

maintainers:
  - Rajendra Nayak <quic_rjendra@quicinc.com>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on X1E80100

  See also: include/dt-bindings/clock/qcom,x1e80100-gcc.h

properties:
  compatible:
    oneOf:
      - items:
          - const: qcom,x1p42100-gcc
          - const: qcom,x1e80100-gcc
      - const: qcom,x1e80100-gcc

  clocks:
    items:
      - description: Board XO source
      - description: Sleep clock source
      - description: PCIe 3 pipe clock
      - description: PCIe 4 pipe clock
      - description: PCIe 5 pipe clock
      - description: PCIe 6a pipe clock
      - description: PCIe 6b pipe clock
      - description: USB4_0 QMPPHY clock source
      - description: USB4_1 QMPPHY clock source
      - description: USB4_2 QMPPHY clock source
      - description: USB4_0 PHY DP0 GMUX clock source
      - description: USB4_0 PHY DP1 GMUX clock source
      - description: USB4_0 PHY PCIE PIPEGMUX clock source
      - description: USB4_0 PHY PIPEGMUX clock source
      - description: USB4_0 PHY SYS PCIE PIPEGMUX clock source
      - description: USB4_1 PHY DP0 GMUX 2 clock source
      - description: USB4_1 PHY DP1 GMUX 2 clock source
      - description: USB4_1 PHY PCIE PIPEGMUX clock source
      - description: USB4_1 PHY PIPEGMUX clock source
      - description: USB4_1 PHY SYS PCIE PIPEGMUX clock source
      - description: USB4_2 PHY DP0 GMUX 2 clock source
      - description: USB4_2 PHY DP1 GMUX 2 clock source
      - description: USB4_2 PHY PCIE PIPEGMUX clock source
      - description: USB4_2 PHY PIPEGMUX clock source
      - description: USB4_2 PHY SYS PCIE PIPEGMUX clock source
      - description: USB4_0 PHY RX 0 clock source
      - description: USB4_0 PHY RX 1 clock source
      - description: USB4_1 PHY RX 0 clock source
      - description: USB4_1 PHY RX 1 clock source
      - description: USB4_2 PHY RX 0 clock source
      - description: USB4_2 PHY RX 1 clock source
      - description: USB4_0 PHY PCIE PIPE clock source
      - description: USB4_0 PHY max PIPE clock source
      - description: USB4_1 PHY PCIE PIPE clock source
      - description: USB4_1 PHY max PIPE clock source
      - description: USB4_2 PHY PCIE PIPE clock source
      - description: USB4_2 PHY max PIPE clock source
      - description: UFS PHY RX Symbol 0 clock source
      - description: UFS PHY RX Symbol 1 clock source
      - description: UFS PHY TX Symbol 0 clock source

  power-domains:
    description:

Annotation

Implementation Notes