Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml

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System
Linux kernel
Corpus path
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
Extension
.yaml
Size
4696 bytes
Lines
153
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas Clock Pulse Generator / Module Standby and Software Reset

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>

description: |
  On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
  and MSSR (Module Standby and Software Reset) blocks are intimately connected,
  and share the same register block.

  They provide the following functionalities:
    - The CPG block generates various core clocks,
    - The MSSR block provides two functions:
        1. Module Standby, providing a Clock Domain to control the clock supply
           to individual SoC devices,
        2. Reset Control, to perform a software reset of individual SoC devices.

properties:
  compatible:
    enum:
      - renesas,r7s9210-cpg-mssr  # RZ/A2
      - renesas,r8a7742-cpg-mssr  # RZ/G1H
      - renesas,r8a7743-cpg-mssr  # RZ/G1M
      - renesas,r8a7744-cpg-mssr  # RZ/G1N
      - renesas,r8a7745-cpg-mssr  # RZ/G1E
      - renesas,r8a77470-cpg-mssr # RZ/G1C
      - renesas,r8a774a1-cpg-mssr # RZ/G2M
      - renesas,r8a774a3-cpg-mssr # RZ/G2M v3.0
      - renesas,r8a774b1-cpg-mssr # RZ/G2N
      - renesas,r8a774c0-cpg-mssr # RZ/G2E
      - renesas,r8a774e1-cpg-mssr # RZ/G2H
      - renesas,r8a7790-cpg-mssr  # R-Car H2
      - renesas,r8a7791-cpg-mssr  # R-Car M2-W
      - renesas,r8a7792-cpg-mssr  # R-Car V2H
      - renesas,r8a7793-cpg-mssr  # R-Car M2-N
      - renesas,r8a7794-cpg-mssr  # R-Car E2
      - renesas,r8a7795-cpg-mssr  # R-Car H3
      - renesas,r8a7796-cpg-mssr  # R-Car M3-W
      - renesas,r8a77961-cpg-mssr # R-Car M3-W+
      - renesas,r8a77965-cpg-mssr # R-Car M3-N
      - renesas,r8a77970-cpg-mssr # R-Car V3M
      - renesas,r8a77980-cpg-mssr # R-Car V3H
      - renesas,r8a77990-cpg-mssr # R-Car E3
      - renesas,r8a77995-cpg-mssr # R-Car D3
      - renesas,r8a779a0-cpg-mssr # R-Car V3U
      - renesas,r8a779f0-cpg-mssr # R-Car S4-8
      - renesas,r8a779g0-cpg-mssr # R-Car V4H
      - renesas,r8a779h0-cpg-mssr # R-Car V4M
      - renesas,r9a09g077-cpg-mssr # RZ/T2H
      - renesas,r9a09g087-cpg-mssr # RZ/N2H

  reg:
    minItems: 1
    items:
      - description: base address of register block 0
      - description: base address of register block 1
    description: base addresses of clock controller. Some controllers
      (like r9a09g077) use two blocks instead of a single one.

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:

Annotation

Implementation Notes