Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

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Linux kernel
Corpus path
Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
Extension
.yaml
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3512 bytes
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120
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>

description: |
  On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
  Standby Mode share the same register block. On RZ/V2M, the functionality is
  similar, but does not have Clock Monitor Registers.

  They provide the following functionalities:
    - The CPG block generates various core clocks,
    - The Module Standby Mode block provides two functions:
        1. Module Standby, providing a Clock Domain to control the clock supply
           to individual SoC devices,
        2. Reset Control, to perform a software reset of individual SoC devices.

properties:
  compatible:
    enum:
      - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five
      - renesas,r9a07g044-cpg # RZ/G2{L,LC}
      - renesas,r9a07g054-cpg # RZ/V2L
      - renesas,r9a08g045-cpg # RZ/G3S
      - renesas,r9a08g046-cpg # RZ/G3L
      - renesas,r9a09g011-cpg # RZ/V2M

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    items:
      - description: Clock source to CPG can be either from external clock
                     input (EXCLK) or crystal oscillator (XIN/XOUT).
      - description: ETH0 TXC clock input
      - description: ETH0 RXC clock input
      - description: ETH1 TXC clock input
      - description: ETH1 RXC clock input

  clock-names:
    minItems: 1
    items:
      - const: extal
      - const: eth0_txc_tx_clk
      - const: eth0_rxc_rx_clk
      - const: eth1_txc_tx_clk
      - const: eth1_rxc_rx_clk

  '#clock-cells':
    description: |
      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
        and a core clock reference, as defined in
        <dt-bindings/clock/r9a0*-cpg.h>,
      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
        a module number, as defined in <dt-bindings/clock/r9a0*-cpg.h>.
    const: 2

  '#power-domain-cells':
    description:
      SoC devices that are part of the CPG/Module Standby Mode Clock Domain and
      can be power-managed through Module Standby should refer to the CPG device
      node in their "power-domains" property, as documented by the generic PM
      Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.

Annotation

Implementation Notes