Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml

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Linux kernel
Corpus path
Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
Extension
.yaml
Size
2503 bytes
Lines
85
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/{G3E,V2H(P),V2N} Clock Pulse Generator (CPG)

maintainers:
  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

description:
  On Renesas RZ/{G3E,V2H(P),V2N} SoCs, the CPG (Clock Pulse Generator) handles
  generation and control of clock signals for the IP modules, generation and
  control of resets, and control over booting, low power consumption and power
  supply domains.

properties:
  compatible:
    enum:
      - renesas,r9a09g047-cpg # RZ/G3E
      - renesas,r9a09g056-cpg # RZ/V2N
      - renesas,r9a09g057-cpg # RZ/V2H

  reg:
    maxItems: 1

  clocks:
    items:
      - description: AUDIO_EXTAL clock input
      - description: RTXIN clock input
      - description: QEXTAL clock input

  clock-names:
    items:
      - const: audio_extal
      - const: rtxin
      - const: qextal

  '#clock-cells':
    description: |
      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
        and a core clock reference, as defined in
        <dt-bindings/clock/renesas,r9a09g0*-cpg.h>,
      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
        a module number.  The module number is calculated as the CLKON register
        offset index multiplied by 16, plus the actual bit in the register
        used to turn the CLK ON. For example, for CGC_GIC_0_GICCLK, the
        calculation is (1 * 16 + 3) = 0x13.
    const: 2

  '#power-domain-cells':
    const: 0

  '#reset-cells':
    description:
      The single reset specifier cell must be the reset number. The reset number
      is calculated as the reset register offset index multiplied by 16, plus the
      actual bit in the register used to reset the specific IP block. For example,
      for SYS_0_PRESETN, the calculation is (3 * 16 + 0) = 0x30.
    const: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#power-domain-cells'
  - '#reset-cells'

Annotation

Implementation Notes