Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml

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Linux kernel
Corpus path
Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml
Extension
.yaml
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2489 bytes
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84
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rk3399-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip RK3399 Clock and Reset Unit

maintainers:
  - Elaine Zhang <zhangqing@rock-chips.com>
  - Heiko Stuebner <heiko@sntech.de>

description: |
  The RK3399 clock controller generates and supplies clock to various
  controllers within the SoC and also implements a reset controller for SoC
  peripherals.
  Each clock is assigned an identifier and client nodes can use this identifier
  to specify the clock which they consume. All available clocks are defined as
  preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
  used in device tree sources. Similar macros exist for the reset sources in
  these files.
  There are several clocks that are generated outside the SoC. It is expected
  that they are defined using standard clock bindings with following
  clock-output-names:
    - "xin24m"           - crystal input                          - required,
    - "xin32k"           - rtc clock                              - optional,
    - "clkin_gmac"       - external GMAC clock                    - optional,
    - "clkin_i2s"        - external I2S clock                     - optional,
    - "pclkin_cif"       - external ISP clock                     - optional,
    - "clk_usbphy0_480m" - output clock of the pll in the usbphy0
    - "clk_usbphy1_480m" - output clock of the pll in the usbphy1

properties:
  compatible:
    enum:
      - rockchip,rk3399-pmucru
      - rockchip,rk3399-cru

  reg:
    maxItems: 1

  "#clock-cells":
    const: 1

  "#reset-cells":
    const: 1

  clocks:
    maxItems: 1

  clock-names:
    const: xin24m

  rockchip,grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the syscon managing the "general register files". It is used
      for GRF muxes, if missing any muxes present in the GRF will not be
      available.

required:
  - compatible
  - reg
  - "#clock-cells"
  - "#reset-cells"

additionalProperties: false

examples:
  - |

Annotation

Implementation Notes