Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml
Extension
.yaml
Size
3669 bytes
Lines
145
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/st,stm32-rcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 Reset Clock Controller

maintainers:
  - Dario Binacchi <dario.binacchi@amarulasolutions.com>

description: |
  The RCC IP is both a reset and a clock controller.
  The reset phandle argument is the bit number within the RCC registers bank,
  starting from RCC base address.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - st,stm32f42xx-rcc
              - st,stm32f746-rcc
              - st,stm32h743-rcc
          - const: st,stm32-rcc
      - items:
          - enum:
              - st,stm32f469-rcc
          - const: st,stm32f42xx-rcc
          - const: st,stm32-rcc
      - items:
          - enum:
              - st,stm32f769-rcc
          - const: st,stm32f746-rcc
          - const: st,stm32-rcc

  reg:
    maxItems: 1

  '#reset-cells':
    const: 1

  '#clock-cells':
    enum: [1, 2]

  clocks:
    minItems: 2
    maxItems: 3

  st,syscfg:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to system configuration controller. It can be used to control the
      power domain circuitry.

  st,ssc-modfreq-hz:
    description:
      The modulation frequency for main PLL (in Hz)

  st,ssc-moddepth-permyriad:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      The modulation rate for main PLL (in permyriad, i.e. 0.01%)
    minimum: 25
    maximum: 200

  st,ssc-modmethod:
    $ref: /schemas/types.yaml#/definitions/string
    description:
      The modulation techniques for main PLL.

Annotation

Implementation Notes