Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml
Extension
.yaml
Size
1091 bytes
Lines
47
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: StarFive JH7110 PLL Clock Generator

description:
  These PLLs are high speed, low jitter frequency synthesizers in the JH7110.
  Each PLL works in integer mode or fraction mode, with configuration
  registers in the sys syscon. So the PLLs node should be a child of
  SYS-SYSCON node.
  The formula for calculating frequency is
  Fvco = Fref * (NI + NF) / M / Q1

maintainers:
  - Xingyu Wu <xingyu.wu@starfivetech.com>

properties:
  compatible:
    const: starfive,jh7110-pll

  clocks:
    maxItems: 1
    description: Main Oscillator (24 MHz)

  '#clock-cells':
    const: 1
    description:
      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.

required:
  - compatible
  - clocks
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    clock-controller {
      compatible = "starfive,jh7110-pll";
      clocks = <&osc>;
      #clock-cells = <1>;
    };

Annotation

Implementation Notes