Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml- Extension
.yaml- Size
- 1802 bytes
- Lines
- 65
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/clock/thead,th1520-clk-ap.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/thead,th1520-clk-ap.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: T-HEAD TH1520 AP sub-system clock controller
description: |
The T-HEAD TH1520 AP sub-system clock controller configures the
CPU, DPU, GMAC and TEE PLLs. Additionally the VO subsystem configures
the clock gates for the HDMI, MIPI and the GPU.
SoC reference manual
https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf
maintainers:
- Jisheng Zhang <jszhang@kernel.org>
- Wei Fu <wefu@redhat.com>
- Drew Fustini <dfustini@tenstorrent.com>
properties:
compatible:
enum:
- thead,th1520-clk-ap
- thead,th1520-clk-vo
reg:
maxItems: 1
clocks:
items:
- description: |
One input clock:
- For "thead,th1520-clk-ap": the clock input must be the 24 MHz
main oscillator.
- For "thead,th1520-clk-vo": the clock input must be the VIDEO_PLL,
which is configured by the AP clock controller. According to the
TH1520 manual, VIDEO_PLL is a Silicon Creations Sigma-Delta PLL
(integer PLL) typically running at 792 MHz (FOUTPOSTDIV), with
a maximum FOUTVCO of 2376 MHz.
"#clock-cells":
const: 1
description:
See <dt-bindings/clock/thead,th1520-clk-ap.h> for valid indices.
required:
- compatible
- reg
- clocks
- "#clock-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/thead,th1520-clk-ap.h>
clock-controller@ef010000 {
compatible = "thead,th1520-clk-ap";
reg = <0xef010000 0x1000>;
clocks = <&osc>;
#clock-cells = <1>;
};
Annotation
- Immediate include surface: `dt-bindings/clock/thead,th1520-clk-ap.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.