Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml- Extension
.yaml- Size
- 1920 bytes
- Lines
- 84
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx clocking wizard
maintainers:
- Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
description:
The clocking wizard is a soft ip clocking block of Xilinx versal. It
reads required input clock frequencies from the devicetree and acts as clock
clock output.
properties:
compatible:
enum:
- xlnx,clocking-wizard
- xlnx,clocking-wizard-v5.2
- xlnx,clocking-wizard-v6.0
- xlnx,versal-clk-wizard
reg:
maxItems: 1
"#clock-cells":
const: 1
clocks:
items:
- description: clock input
- description: axi clock
clock-names:
items:
- const: clk_in1
- const: s_axi_aclk
xlnx,static-config:
$ref: /schemas/types.yaml#/definitions/flag
description:
Indicate whether the core has been configured without support for dynamic
runtime reconfguration of the clocking primitive MMCM/PLL.
xlnx,speed-grade:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2, 3]
description:
Speed grade of the device. Higher the speed grade faster is the FPGA device.
xlnx,nr-outputs:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1
maximum: 8
description:
Number of outputs.
required:
- compatible
- reg
- "#clock-cells"
- clocks
- clock-names
- xlnx,speed-grade
- xlnx,nr-outputs
additionalProperties: false
Annotation
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.