Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml- Extension
.yaml- Size
- 6071 bytes
- Lines
- 185
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/gpio/gpio.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/connector/pcie-m2-e-connector.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: PCIe M.2 Mechanical Key E Connector
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
description:
A PCIe M.2 E connector node represents a physical PCIe M.2 Mechanical Key E
connector. Mechanical Key E connectors are used to connect Wireless
Connectivity devices including combinations of Wi-Fi, BT, NFC to the host
machine over interfaces like PCIe/SDIO, USB/UART+PCM, and I2C.
properties:
compatible:
const: pcie-m2-e-connector
vpcie3v3-supply:
description: A phandle to the regulator for 3.3v supply.
vpcie1v8-supply:
description: A phandle to the regulator for VIO 1.8v supply.
i2c-parent:
$ref: /schemas/types.yaml#/definitions/phandle
description: I2C interface
clocks:
description: 32.768 KHz Suspend Clock (SUSCLK) input from the host system to
the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.1 for
more details.
maxItems: 1
w-disable1-gpios:
description: GPIO output to W_DISABLE1# signal. This signal is used by the
host system to disable WiFi radio in the M.2 card. Refer, PCI Express M.2
Specification r4.0, sec 3.1.12.3 for more details.
maxItems: 1
w-disable2-gpios:
description: GPIO output to W_DISABLE2# signal. This signal is used by the
host system to disable BT radio in the M.2 card. Refer, PCI Express M.2
Specification r4.0, sec 3.1.12.3 for more details.
maxItems: 1
viocfg-gpios:
description: GPIO input to IO voltage configuration (VIO_CFG) signal. The
card drives this signal to indicate to the host system whether the card
supports an independent IO voltage domain for sideband signals. Refer,
PCI Express M.2 Specification r4.0, sec 3.1.15.1 for more details.
maxItems: 1
uart-wake-gpios:
description: GPIO input to UART_WAKE# signal. The card asserts this signal
to wake the host system and initiate UART interface communication. Refer,
PCI Express M.2 Specification r4.0, sec 3.1.8.1 for more details.
maxItems: 1
sdio-wake-gpios:
description: GPIO input to SDIO_WAKE# signal. The card asserts this signal
to wake the host system and initiate SDIO interface communication. Refer,
PCI Express M.2 Specification r4.0, sec 3.1.7 for more details.
maxItems: 1
sdio-reset-gpios:
description: GPIO output to SDIO_RESET# signal. This signal is used by the
Annotation
- Immediate include surface: `dt-bindings/gpio/gpio.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.