Documentation/devicetree/bindings/cpufreq/qcom,shikra-epss.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/cpufreq/qcom,shikra-epss.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/cpufreq/qcom,shikra-epss.yaml- Extension
.yaml- Size
- 2157 bytes
- Lines
- 97
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/clock/qcom,rpmcc.hdt-bindings/interrupt-controller/arm-gic.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/cpufreq/qcom,shikra-epss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Shikra SoC EPSS
maintainers:
- Imran Shaik <imran.shaik@oss.qualcomm.com>
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
EPSS is a hardware engine used by some Qualcomm SoCs to manage
frequency in hardware. It is capable of controlling frequency for
multiple clusters.
The Qualcomm Shikra SoC EPSS supports up to 12 frequency lookup table
(LUT) entries.
properties:
compatible:
enum:
- qcom,shikra-epss
reg:
items:
- description: Frequency domain 0 register region
- description: Frequency domain 1 register region
reg-names:
items:
- const: freq-domain0
- const: freq-domain1
clocks:
items:
- description: XO Clock
- description: GPLL0 Clock
clock-names:
items:
- const: xo
- const: alternate
interrupts:
items:
- description: IRQ line for DCVSH 0
- description: IRQ line for DCVSH 1
interrupt-names:
items:
- const: dcvsh-irq-0
- const: dcvsh-irq-1
'#freq-domain-cells':
const: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
- interrupt-names
- '#freq-domain-cells'
- '#clock-cells'
Annotation
- Immediate include surface: `dt-bindings/clock/qcom,rpmcc.h`, `dt-bindings/interrupt-controller/arm-gic.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.