Documentation/devicetree/bindings/crypto/fsl,sec-v4.0.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/crypto/fsl,sec-v4.0.yaml- Extension
.yaml- Size
- 9016 bytes
- Lines
- 319
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: GPL-2.0
# Copyright (C) 2008-2011 Freescale Semiconductor Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale SEC 4
maintainers:
- '"Horia Geantă" <horia.geanta@nxp.com>'
- Pankaj Gupta <pankaj.gupta@nxp.com>
- Gaurav Jain <gaurav.jain@nxp.com>
description: |
NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
Accelerator and Assurance Module (CAAM).
SEC 4 h/w can process requests from 2 types of sources.
1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
2. Job Rings (HW interface between cores & SEC 4 registers).
High Speed Data Path Configuration:
HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
such as the P4080. The number of simultaneous dequeues the QI can make is
equal to the number of Descriptor Controller (DECO) engines in a particular
SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
dequeue from 5 subportals simultaneously.
Job Ring Data Path Configuration:
Each JR is located on a separate 4k page, they may (or may not) be made visible
in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
properties:
compatible:
oneOf:
- items:
- enum:
- fsl,sec-v5.4
- fsl,sec-v6.0
- const: fsl,sec-v5.0
- const: fsl,sec-v4.0
- items:
- enum:
- fsl,imx6ul-caam
- fsl,imx8qm-caam
- fsl,imx8qxp-caam
- fsl,sec-v5.0
- const: fsl,sec-v4.0
- const: fsl,sec-v4.0
reg:
maxItems: 1
ranges:
maxItems: 1
'#address-cells':
enum: [1, 2]
'#size-cells':
enum: [1, 2]
clocks:
minItems: 1
maxItems: 4
Annotation
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.