Documentation/devicetree/bindings/crypto/hisilicon,hip06-sec.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/crypto/hisilicon,hip06-sec.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/crypto/hisilicon,hip06-sec.yaml- Extension
.yaml- Size
- 4923 bytes
- Lines
- 135
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/hisilicon,hip06-sec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hisilicon hip06/hip07 Security Accelerator
maintainers:
- Jonathan Cameron <Jonathan.Cameron@huawei.com>
properties:
compatible:
enum:
- hisilicon,hip06-sec
- hisilicon,hip07-sec
reg:
items:
- description: Registers for backend processing engines
- description: Registers for common functionality
- description: Registers for queue 0
- description: Registers for queue 1
- description: Registers for queue 2
- description: Registers for queue 3
- description: Registers for queue 4
- description: Registers for queue 5
- description: Registers for queue 6
- description: Registers for queue 7
- description: Registers for queue 8
- description: Registers for queue 9
- description: Registers for queue 10
- description: Registers for queue 11
- description: Registers for queue 12
- description: Registers for queue 13
- description: Registers for queue 14
- description: Registers for queue 15
interrupts:
items:
- description: SEC unit error queue interrupt
- description: Completion interrupt for queue 0
- description: Error interrupt for queue 0
- description: Completion interrupt for queue 1
- description: Error interrupt for queue 1
- description: Completion interrupt for queue 2
- description: Error interrupt for queue 2
- description: Completion interrupt for queue 3
- description: Error interrupt for queue 3
- description: Completion interrupt for queue 4
- description: Error interrupt for queue 4
- description: Completion interrupt for queue 5
- description: Error interrupt for queue 5
- description: Completion interrupt for queue 6
- description: Error interrupt for queue 6
- description: Completion interrupt for queue 7
- description: Error interrupt for queue 7
- description: Completion interrupt for queue 8
- description: Error interrupt for queue 8
- description: Completion interrupt for queue 9
- description: Error interrupt for queue 9
- description: Completion interrupt for queue 10
- description: Error interrupt for queue 10
- description: Completion interrupt for queue 11
- description: Error interrupt for queue 11
- description: Completion interrupt for queue 12
- description: Error interrupt for queue 12
- description: Completion interrupt for queue 13
- description: Error interrupt for queue 13
- description: Completion interrupt for queue 14
Annotation
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.