Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml- Extension
.yaml- Size
- 3796 bytes
- Lines
- 165
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/interrupt-controller/arm-gic.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence MHDP8546 bridge
maintainers:
- Swapnil Jakhade <sjakhade@cadence.com>
- Yuti Amonkar <yamonkar@cadence.com>
properties:
compatible:
enum:
- cdns,mhdp8546
- ti,j721e-mhdp8546
reg:
minItems: 1
items:
- description:
Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
The AUX and PMA registers are not part of this range, they are instead
included in the associated PHY.
- description:
Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs.
- description:
Register block of mhdptx sapb registers.
reg-names:
minItems: 1
items:
- const: mhdptx
- const: j721e-intg
- const: mhdptx-sapb
clocks:
maxItems: 1
description:
DP bridge clock, used by the IP to know how to translate a number of
clock cycles into a time (which is used to comply with DP standard timings
and delays).
phys:
maxItems: 1
description:
phandle to the DisplayPort PHY.
phy-names:
items:
- const: dpphy
power-domains:
maxItems: 1
interrupts:
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description:
First input port representing the DP bridge input.
port@1:
$ref: /schemas/graph.yaml#/properties/port
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/arm-gic.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.