Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc.yaml

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Linux kernel
Corpus path
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc.yaml
Extension
.yaml
Size
8834 bytes
Lines
237
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX8qxp Display Controller

description: |
  The Freescale i.MX8qxp Display Controller(DC) is comprised of three main
  components that include a blit engine for 2D graphics accelerations, display
  controller for display output processing, as well as a command sequencer.

                                  Display buffers              Source buffers
                                 (AXI read master)            (AXI read master)
                                  | .......... |                  | | |
      +---------------------------+------------+------------------+-+-+------+
      | Display Controller (DC)   | .......... |                  | | |      |
      |                           |            |                  | | |      |
      |   @@@@@@@@@@@  +----------+------------+------------+     | | |      |
  A   |  | Command   | |          V            V            |     | | |      |
  X <-+->| Sequencer | |    @@@@@@@@@@@@@@@@@@@@@@@@@@@@    |     V V V      |
  I   |  | (AXI CLK) | |   |                            |   |   @@@@@@@@@@   |
      |   @@@@@@@@@@@  |   |       Pixel Engine         |   |  |          |  |
      |       |        |   |         (AXI CLK)          |   |  |          |  |
      |       V        |    @@@@@@@@@@@@@@@@@@@@@@@@@@@@    |  |          |  |
  A   |   ***********  |       |   |            |   |       |  |   Blit   |  |
  H <-+->| Configure | |       V   V            V   V       |  |  Engine  |  |
  B   |  | (CFG CLK) | |    00000000000      11111111111    |  | (AXI CLK)|  |
      |   ***********  |   |  Display  |    |  Display  |   |  |          |  |
      |                |   |  Engine   |    |  Engine   |   |  |          |  |
      |                |   | (Disp CLK)|    | (Disp CLK)|   |  |          |  |
      |   @@@@@@@@@@@  |    00000000000      11111111111    |   @@@@@@@@@@   |
  I   |  |  Common   | |         |                |         |       |        |
  R <-+--|  Control  | |         |    Display     |         |       |        |
  Q   |  | (AXI CLK) | |         |   Controller   |         |       |        |
      |   @@@@@@@@@@@  +------------------------------------+       |        |
      |                          |                |       ^         |        |
      +--------------------------+----------------+-------+---------+--------+
              ^                  |                |       |         |
              |                  V                V       |         V
       Clocks & Resets        Display          Display  Panic   Destination
                              Output0          Output1 Control    buffer
                                                              (AXI write master)

maintainers:
  - Liu Ying <victor.liu@nxp.com>

properties:
  compatible:
    const: fsl,imx8qxp-dc

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 2

  reset-names:
    items:
      - const: axi
      - const: cfg

  power-domains:
    maxItems: 1

  "#address-cells":

Annotation

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