Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml

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System
Linux kernel
Corpus path
Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
Extension
.yaml
Size
3207 bytes
Lines
108
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: mediatek display DSC controller

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Philipp Zabel <p.zabel@pengutronix.de>

description: |
  The DSC standard is a specification of the algorithms used for
  compressing and decompressing image display streams, including
  the specification of the syntax and semantics of the compressed
  video bit stream. DSC is designed for real-time systems with
  real-time compression, transmission, decompression and Display.

properties:
  compatible:
    oneOf:
      - enum:
          - mediatek,mt8195-disp-dsc
      - items:
          - const: mediatek,mt8188-disp-dsc
          - const: mediatek,mt8195-disp-dsc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: DSC Wrapper Clock

  power-domains:
    description: A phandle and PM domain specifier as defined by bindings of
      the power controller specified by phandle. See
      Documentation/devicetree/bindings/power/power-domain.yaml for details.

  mediatek,gce-client-reg:
    description:
      The register of client driver can be configured by gce with 4 arguments
      defined in this property, such as phandle of gce, subsys id,
      register offset and size.
      Each subsys id is mapping to a base address of display function blocks
      register which is defined in the gce header
      include/dt-bindings/gce/<chip>-gce.h.
    $ref: /schemas/types.yaml#/definitions/phandle-array
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports
    description:
      Input and output ports can have multiple endpoints, each of those
      connects to either the primary, secondary, etc, display pipeline.

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Display Stream Compression input, usually from one of the DITHER
          or MERGE blocks.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:

Annotation

Implementation Notes