Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml

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Linux kernel
Corpus path
Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
Extension
.yaml
Size
2932 bytes
Lines
115
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,split.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek display split

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Philipp Zabel <p.zabel@pengutronix.de>

description: |
  Mediatek display split, namely SPLIT, is used to split stream to two
  encoders.
  SPLIT device node must be siblings to the central MMSYS_CONFIG node.
  For a description of the MMSYS_CONFIG binding, see
  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
  for details.

properties:
  compatible:
    oneOf:
      - enum:
          - mediatek,mt8173-disp-split
          - mediatek,mt8195-mdp3-split
      - items:
          - const: mediatek,mt6795-disp-split
          - const: mediatek,mt8173-disp-split

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    description: A phandle and PM domain specifier as defined by bindings of
      the power controller specified by phandle. See
      Documentation/devicetree/bindings/power/power-domain.yaml for details.
    maxItems: 1

  mediatek,gce-client-reg:
    description:
      The register of display function block to be set by gce. There are 4 arguments,
      such as gce node, subsys id, offset and register size. The subsys id that is
      mapping to the register of display function blocks is defined in the gce header
      include/dt-bindings/gce/<chip>-gce.h of each chips.
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      items:
        - description: phandle of GCE
        - description: GCE subsys id
        - description: register offset
        - description: register size
    maxItems: 1

  clocks:
    items:
      - description: SPLIT Clock
      - description: Used for interfacing with the HDMI RX signal source.
      - description: Paired with receiving HDMI RX metadata.
    minItems: 1

required:
  - compatible
  - reg
  - power-domains
  - clocks

Annotation

Implementation Notes