Documentation/devicetree/bindings/display/msm/gmu.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/display/msm/gmu.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/display/msm/gmu.yaml- Extension
.yaml- Size
- 11288 bytes
- Lines
- 454
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/clock/qcom,gpucc-sdm845.hdt-bindings/clock/qcom,gcc-sdm845.hdt-bindings/interrupt-controller/irq.hdt-bindings/interrupt-controller/arm-gic.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: GPL-2.0-only
# Copyright 2019-2020, The Linux Foundation, All Rights Reserved
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/gmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: GMU attached to certain Adreno GPUs
maintainers:
- Rob Clark <robdclark@gmail.com>
description: |
These bindings describe the Graphics Management Unit (GMU) that is attached
to members of the Adreno A6xx GPU family. The GMU provides on-device power
management and support to improve power efficiency and reduce the load on
the CPU.
properties:
compatible:
oneOf:
- items:
- pattern: '^qcom,adreno-gmu-[6-8][0-9][0-9]\.[0-9]$'
- const: qcom,adreno-gmu
- items:
- pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$'
- const: qcom,adreno-gmu
- const: qcom,adreno-gmu-wrapper
reg:
minItems: 1
maxItems: 4
reg-names:
minItems: 1
maxItems: 4
clocks:
minItems: 4
maxItems: 7
clock-names:
minItems: 4
maxItems: 7
interrupts:
items:
- description: GMU HFI interrupt
- description: GMU interrupt
interrupt-names:
items:
- const: hfi
- const: gmu
power-domains:
items:
- description: CX power domain
- description: GX power domain
power-domain-names:
items:
- const: cx
- const: gx
iommus:
maxItems: 1
qcom,qmp:
Annotation
- Immediate include surface: `dt-bindings/clock/qcom,gpucc-sdm845.h`, `dt-bindings/clock/qcom,gcc-sdm845.h`, `dt-bindings/interrupt-controller/irq.h`, `dt-bindings/interrupt-controller/arm-gic.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.