Documentation/devicetree/bindings/display/msm/qcom,adreno-rgmu.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/display/msm/qcom,adreno-rgmu.yaml

File Facts

System: Linux kernel
Corpus path: Documentation/devicetree/bindings/display/msm/qcom,adreno-rgmu.yaml
Extension: .yaml
Size: 3096 bytes
Lines: 127
Domain: Support Tooling And Documentation
Bucket: Documentation
Inferred role: Support Tooling And Documentation: configuration, schema, or hardware description
Status: atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

dt-bindings/clock/qcom,qcs615-gpucc.h
dt-bindings/clock/qcom,qcs615-gcc.h
dt-bindings/interrupt-controller/arm-gic.h
dt-bindings/power/qcom,rpmhpd.h

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
%YAML 1.2
---

$id: http://devicetree.org/schemas/display/msm/qcom,adreno-rgmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: RGMU attached to certain Adreno GPUs

maintainers:
  - Rob Clark <robin.clark@oss.qualcomm.com>

description:
  RGMU (Reduced Graphics Management Unit) IP is present in some GPUs that
  belong to Adreno A6xx family. It is a small state machine that helps to
  toggle the GX GDSC (connected to CX rail) to implement IFPC feature and save
  power.

properties:
  compatible:
    items:
      - const: qcom,adreno-rgmu-612.0
      - const: qcom,adreno-rgmu

  reg:
    items:
      - description: Core RGMU registers

  clocks:
    items:
      - description: GMU clock
      - description: GPU CX clock
      - description: GPU AXI clock
      - description: GPU MEMNOC clock
      - description: GPU SMMU vote clock

  clock-names:
    items:
      - const: gmu
      - const: cxo
      - const: axi
      - const: memnoc
      - const: smmu_vote

  power-domains:
    items:
      - description: CX GDSC power domain
      - description: GX GDSC power domain

  power-domain-names:
    items:
      - const: cx
      - const: gx

  interrupts:
    items:
      - description: GMU OOB interrupt
      - description: GMU interrupt

  interrupt-names:
    items:
      - const: oob
      - const: gmu

  operating-points-v2: true
  opp-table:
    type: object

required:

Annotation

Immediate include surface: `dt-bindings/clock/qcom,qcs615-gpucc.h`, `dt-bindings/clock/qcom,qcs615-gcc.h`, `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/power/qcom,rpmhpd.h`.
Atlas domain: Support Tooling And Documentation / Documentation.
Implementation status: atlas-only.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.