Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml- Extension
.yaml- Size
- 3841 bytes
- Lines
- 171
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/clock/rockchip,rk3588-cru.hdt-bindings/phy/phy.hdt-bindings/interrupt-controller/arm-gic.hdt-bindings/interrupt-controller/irq.hdt-bindings/power/rk3588-power.hdt-bindings/reset/rockchip,rk3588-cru.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-dp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip DW DisplayPort Transmitter
maintainers:
- Andy Yan <andy.yan@rock-chips.com>
description: |
The Rockchip RK3588 SoC integrates the Synopsys DesignWare DPTX controller
which is compliant with the DisplayPort Specification Version 1.4 with the
following features:
* DisplayPort 1.4a
* Main Link: 1/2/4 lanes
* Main Link Support 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps
* AUX channel 1Mbps
* Single Stream Transport(SST)
* Multistream Transport (MST)
* Type-C support (alternate mode)
* HDCP 2.2, HDCP 1.3
* Supports up to 8/10 bits per color component
* Supports RBG, YCbCr4:4:4, YCbCr4:2:2, YCbCr4:2:0
* Pixel clock up to 594MHz
* I2S, SPDIF audio interface
properties:
compatible:
enum:
- rockchip,rk3576-dp
- rockchip,rk3588-dp
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 3
items:
- description: Peripheral/APB bus clock
- description: DisplayPort AUX clock
- description: HDCP clock
- description: I2S interface clock
- description: SPDIF interfce clock
clock-names:
minItems: 3
items:
- const: apb
- const: aux
- const: hdcp
- const: i2s
- const: spdif
phys:
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: Video port for RGB/YUV input.
Annotation
- Immediate include surface: `dt-bindings/clock/rockchip,rk3588-cru.h`, `dt-bindings/phy/phy.h`, `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/interrupt-controller/irq.h`, `dt-bindings/power/rk3588-power.h`, `dt-bindings/reset/rockchip,rk3588-cru.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.