Documentation/devicetree/bindings/display/samsung/samsung,exynos7-decon.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/display/samsung/samsung,exynos7-decon.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/display/samsung/samsung,exynos7-decon.yaml
Extension
.yaml
Size
3851 bytes
Lines
143
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/samsung/samsung,exynos7-decon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos7 SoC Display and Enhancement Controller (DECON)

maintainers:
  - Inki Dae <inki.dae@samsung.com>
  - Seung-Woo Kim <sw0312.kim@samsung.com>
  - Kyungmin Park <kyungmin.park@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>

description: |
  DECON (Display and Enhancement Controller) is the Display Controller for the
  Exynos7 series of SoCs which transfers the image data from a video memory
  buffer to an external LCD interface.

properties:
  compatible:
    enum:
      - samsung,exynos7-decon
      - samsung,exynos7870-decon

  clocks:
    maxItems: 4

  clock-names:
    items:
      - const: pclk_decon0
      - const: aclk_decon0
      - const: decon0_eclk
      - const: decon0_vclk

  display-timings:
    $ref: ../panel/display-timings.yaml#

  i80-if-timings:
    type: object
    additionalProperties: false
    description: timing configuration for lcd i80 interface support
    properties:
      cs-setup:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Clock cycles for the active period of address signal is enabled until
          chip select is enabled.
        default: 0

      wr-active:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Clock cycles for the active period of CS is enabled.
        default: 1

      wr-hold:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Clock cycles for the active period of CS is disabled until write
          signal is disabled.
        default: 0

      wr-setup:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Clock cycles for the active period of CS signal is enabled until
          write signal is enabled.
        default: 0

Annotation

Implementation Notes