Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml- Extension
.yaml- Size
- 6393 bytes
- Lines
- 208
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/interrupt-controller/arm-gic.hdt-bindings/interrupt-controller/irq.hdt-bindings/soc/ti,sci_pm_domain.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 Texas Instruments Incorporated
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments J721E Display Subsystem
maintainers:
- Jyri Sarha <jsarha@ti.com>
- Tomi Valkeinen <tomi.valkeinen@ti.com>
description: |
The J721E TI Keystone Display SubSystem with four output ports and
four video planes. There is two full video planes and two "lite
planes" without scaling support. The video ports can be connected to
the SoC's DPI pins or to integrated display bridges on the SoC.
properties:
compatible:
const: ti,j721e-dss
reg:
items:
- description: common_m DSS Master common
- description: common_s0 DSS Shared common 0
- description: common_s1 DSS Shared common 1
- description: common_s2 DSS Shared common 2
- description: VIDL1 light video plane 1
- description: VIDL2 light video plane 2
- description: VID1 video plane 1
- description: VID1 video plane 2
- description: OVR1 overlay manager for vp1
- description: OVR2 overlay manager for vp2
- description: OVR3 overlay manager for vp3
- description: OVR4 overlay manager for vp4
- description: VP1 video port 1
- description: VP2 video port 2
- description: VP3 video port 3
- description: VP4 video port 4
- description: WB Write Back
reg-names:
items:
- const: common_m
- const: common_s0
- const: common_s1
- const: common_s2
- const: vidl1
- const: vidl2
- const: vid1
- const: vid2
- const: ovr1
- const: ovr2
- const: ovr3
- const: ovr4
- const: vp1
- const: vp2
- const: vp3
- const: vp4
- const: wb
clocks:
items:
- description: fck DSS functional clock
- description: vp1 Video Port 1 pixel clock
- description: vp2 Video Port 2 pixel clock
- description: vp3 Video Port 3 pixel clock
- description: vp4 Video Port 4 pixel clock
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/interrupt-controller/irq.h`, `dt-bindings/soc/ti,sci_pm_domain.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.