Documentation/devicetree/bindings/display/xylon,logicvc-display.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/display/xylon,logicvc-display.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/display/xylon,logicvc-display.yaml- Extension
.yaml- Size
- 8554 bytes
- Lines
- 302
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/interrupt-controller/irq.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 Bootlin
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xylon LogiCVC display controller
maintainers:
- Paul Kocialkowski <paul.kocialkowski@bootlin.com>
description: |
The Xylon LogiCVC is a display controller that supports multiple layers.
It is usually implemented as programmable logic and was optimized for use
with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
Because the controller is intended for use in a FPGA, most of the
configuration of the controller takes place at logic configuration bitstream
synthesis time. As a result, many of the device-tree bindings are meant to
reflect the synthesis configuration and must not be configured differently.
Matching synthesis parameters are provided when applicable.
Layers are declared in the "layers" sub-node and have dedicated configuration.
In version 3 of the controller, each layer has fixed memory offset and address
starting from the video memory base address for its framebuffer. In version 4,
framebuffers are configured with a direct memory address instead.
properties:
compatible:
enum:
- xylon,logicvc-3.02.a-display
- xylon,logicvc-4.01.a-display
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 4
clock-names:
minItems: 1
items:
# vclk is required and must be provided as first item.
- const: vclk
# Other clocks are optional and can be provided in any order.
- enum:
- vclk2
- lvdsclk
- lvdsclkn
- enum:
- vclk2
- lvdsclk
- lvdsclkn
- enum:
- vclk2
- lvdsclk
- lvdsclkn
interrupts:
maxItems: 1
memory-region:
maxItems: 1
xylon,display-interface:
enum:
# Parallel RGB interface (C_DISPLAY_INTERFACE == 0)
- parallel-rgb
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/irq.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.