Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml

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System
Linux kernel
Corpus path
Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml
Extension
.yaml
Size
5232 bytes
Lines
142
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 DMA3 Controller

description: |
  The STM32 DMA3 is a direct memory access controller with different features
  depending on its hardware configuration.
  It is either called LPDMA (Low Power), GPDMA (General Purpose) or HPDMA (High
  Performance).
  Its hardware configuration registers allow to dynamically expose its features.

  GPDMA and HPDMA support 16 independent DMA channels, while only 4 for LPDMA.
  GPDMA and HPDMA support 256 DMA requests from peripherals, 8 for LPDMA.

  Bindings are generic for these 3 STM32 DMA3 configurations.

  DMA clients connected to the STM32 DMA3 controller must use the format
  described in "#dma-cells" property description below, using a three-cell
  specifier for each channel.

maintainers:
  - Amelie Delaunay <amelie.delaunay@foss.st.com>

allOf:
  - $ref: /schemas/dma/dma-controller.yaml#

properties:
  compatible:
    const: st,stm32mp25-dma3

  reg:
    maxItems: 1

  interrupts:
    minItems: 4
    maxItems: 16
    description:
      Should contain all of the per-channel DMA interrupts in ascending order
      with respect to the DMA channel index.

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  power-domains:
    maxItems: 1

  "#dma-cells":
    const: 3
    description: |
      Specifies the number of cells needed to provide DMA controller specific
      information.
      The first cell is the request line number.
      The second cell is a 32-bit mask specifying the DMA channel requirements:
        -bit 0-1: The priority level
          0x0: low priority, low weight
          0x1: low priority, mid weight
          0x2: low priority, high weight
          0x3: high priority
        -bit 4-7: The FIFO requirement for queuing source/destination transfers
          0x0: no FIFO requirement/any channel can fit
          0x2: FIFO of 8 bytes (2^2+1)
          0x4: FIFO of 32 bytes (2^4+1)
          0x6: FIFO of 128 bytes (2^6+1)

Annotation

Implementation Notes