Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml- Extension
.yaml- Size
- 3151 bytes
- Lines
- 132
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dpll/microchip,zl30731.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip Azurite DPLL device
maintainers:
- Ivan Vecera <ivecera@redhat.com>
description:
Microchip Azurite DPLL (ZL3073x) is a family of DPLL devices that
provides up to 5 independent DPLL channels, up to 10 differential or
single-ended inputs and 10 differential or 20 single-ended outputs.
These devices support both I2C and SPI interfaces.
properties:
compatible:
enum:
- microchip,zl30731
- microchip,zl30732
- microchip,zl30733
- microchip,zl30734
- microchip,zl30735
reg:
maxItems: 1
required:
- compatible
- reg
allOf:
- $ref: /schemas/dpll/dpll-device.yaml#
- $ref: /schemas/spi/spi-peripheral-props.yaml#
unevaluatedProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
dpll@70 {
compatible = "microchip,zl30732";
reg = <0x70>;
dpll-types = "pps", "eec";
input-pins {
#address-cells = <1>;
#size-cells = <0>;
sync0: pin@0 { /* REF0P - 1 PPS sync source */
reg = <0>;
connection-type = "ext";
label = "SMA1";
supported-frequencies-hz = /bits/ 64 <1>;
};
pin@1 { /* REF0N - clock source, can pair with sync0 */
reg = <1>;
connection-type = "ext";
label = "SMA2";
supported-frequencies-hz = /bits/ 64 <10000 10000000>;
ref-sync-sources = <&sync0>;
};
};
Annotation
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.