Documentation/devicetree/bindings/fpga/fpga-region.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/fpga/fpga-region.yaml

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Linux kernel
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Documentation/devicetree/bindings/fpga/fpga-region.yaml
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.yaml
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Support Tooling And Documentation
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Documentation
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Support Tooling And Documentation: configuration, schema, or hardware description
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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: FPGA Region

maintainers:
  - Michal Simek <michal.simek@amd.com>

description: |
  CONTENTS
   - Introduction
   - Terminology
   - Sequence
   - FPGA Region
   - Supported Use Models
   - Constraints

  Introduction
  ============

  FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in
  the Device Tree.  FPGA Regions provide a way to program FPGAs under device tree
  control.

  The documentation hits some of the high points of FPGA usage and
  attempts to include terminology used by both major FPGA manufacturers.  This
  document isn't a replacement for any manufacturers specifications for FPGA
  usage.

  Terminology
  ===========

  Full Reconfiguration
   * The entire FPGA is programmed.

  Partial Reconfiguration (PR)
   * A section of an FPGA is reprogrammed while the rest of the FPGA is not
     affected.
   * Not all FPGA's support PR.

  Partial Reconfiguration Region (PRR)
   * Also called a "reconfigurable partition"
   * A PRR is a specific section of an FPGA reserved for reconfiguration.
   * A base (or static) FPGA image may create a set of PRR's that later may
     be independently reprogrammed many times.
   * The size and specific location of each PRR is fixed.
   * The connections at the edge of each PRR are fixed.  The image that is loaded
     into a PRR must fit and must use a subset of the region's connections.
   * The busses within the FPGA are split such that each region gets its own
     branch that may be gated independently.

  Persona
   * Also called a "partial bit stream"
   * An FPGA image that is designed to be loaded into a PRR.  There may be
     any number of personas designed to fit into a PRR, but only one at a time
     may be loaded.
   * A persona may create more regions.

  FPGA Bridge
   * FPGA Bridges gate bus signals between a host and FPGA.
   * FPGA Bridges should be disabled while the FPGA is being programmed to
     prevent spurious signals on the cpu bus and to the soft logic.
   * FPGA bridges may be actual hardware or soft logic on an FPGA.
   * During Full Reconfiguration, hardware bridges between the host and FPGA
     will be disabled.
   * During Partial Reconfiguration of a specific region, that region's bridge
     will be used to gate the busses.  Traffic to other regions is not affected.

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