Documentation/devicetree/bindings/gpio/ti,keystone-dsp-gpio.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/gpio/ti,keystone-dsp-gpio.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/gpio/ti,keystone-dsp-gpio.yaml- Extension
.yaml- Size
- 1704 bytes
- Lines
- 66
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/ti,keystone-dsp-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Keystone 2 DSP GPIO controller
maintainers:
- Grygorii Strashko <grygorii.strashko@ti.com>
description: |
HOST OS userland running on ARM can send interrupts to DSP cores using
the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
This is one of the component used by the IPC mechanism used on Keystone SOCs.
For example TCI6638K2K SoC has 8 DSP GPIO controllers:
- 8 for C66x CorePacx CPUs 0-7
Keystone 2 DSP GPIO controller has specific features:
- each GPIO can be configured only as output pin;
- setting GPIO value to 1 causes IRQ generation on target DSP core;
- reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still
pending.
properties:
compatible:
const: ti,keystone-dsp-gpio
reg:
maxItems: 1
gpio-controller: true
'#gpio-cells':
const: 2
gpio,syscon-dev:
description:
Phandle and offset of device's specific registers within the syscon state
control registers
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to syscon
- description: register offset within state control registers
required:
- compatible
- reg
- gpio-controller
- '#gpio-cells'
- gpio,syscon-dev
additionalProperties: false
examples:
- |
gpio@240 {
compatible = "ti,keystone-dsp-gpio";
reg = <0x240 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio,syscon-dev = <&devctrl 0x240>;
};
Annotation
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.