Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml- Extension
.yaml- Size
- 2596 bytes
- Lines
- 107
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/clock/tegra186-clock.hdt-bindings/interrupt-controller/arm-gic.hdt-bindings/memory/tegra186-mc.hdt-bindings/power/tegra186-powergate.hdt-bindings/reset/tegra186-reset.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra NVDEC
description: |
NVDEC is the hardware video decoder present on NVIDIA Tegra210
and newer chips. It is located on the Host1x bus and typically
programmed through Host1x channels.
maintainers:
- Thierry Reding <treding@gmail.com>
- Mikko Perttunen <mperttunen@nvidia.com>
properties:
$nodename:
pattern: "^nvdec@[0-9a-f]*$"
compatible:
enum:
- nvidia,tegra210-nvdec
- nvidia,tegra186-nvdec
- nvidia,tegra194-nvdec
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: nvdec
resets:
maxItems: 1
reset-names:
items:
- const: nvdec
power-domains:
maxItems: 1
iommus:
maxItems: 1
dma-coherent: true
interconnects:
items:
- description: DMA read memory client
- description: DMA read 2 memory client
- description: DMA write memory client
interconnect-names:
items:
- const: dma-mem
- const: read-1
- const: write
nvidia,host1x-class:
description: |
Host1x class of the engine, used to specify the targeted engine
when programming the engine through Host1x channels or when
configuring engine-specific behavior in Host1x.
default: 0xf0
Annotation
- Immediate include surface: `dt-bindings/clock/tegra186-clock.h`, `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/memory/tegra186-mc.h`, `dt-bindings/power/tegra186-powergate.h`, `dt-bindings/reset/tegra186-reset.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.