Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml

File Facts

System: Linux kernel
Corpus path: Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml
Extension: .yaml
Size: 3154 bytes
Lines: 136
Domain: Support Tooling And Documentation
Bucket: Documentation
Inferred role: Support Tooling And Documentation: configuration, schema, or hardware description
Status: atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

dt-bindings/clock/tegra186-clock.h
dt-bindings/memory/tegra186-mc.h
dt-bindings/power/tegra186-powergate.h
dt-bindings/reset/tegra186-reset.h

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra NVENC

description: |
  NVENC is the hardware video encoder present on NVIDIA Tegra210
  and newer chips. It is located on the Host1x bus and typically
  programmed through Host1x channels.

maintainers:
  - Thierry Reding <treding@gmail.com>
  - Mikko Perttunen <mperttunen@nvidia.com>

properties:
  $nodename:
    pattern: "^nvenc@[0-9a-f]*$"

  compatible:
    enum:
      - nvidia,tegra210-nvenc
      - nvidia,tegra186-nvenc
      - nvidia,tegra194-nvenc

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: nvenc

  resets:
    maxItems: 1

  reset-names:
    items:
      - const: nvenc

  power-domains:
    maxItems: 1

  iommus:
    maxItems: 1

  dma-coherent: true

  interconnects:
    minItems: 2
    maxItems: 3

  interconnect-names:
    minItems: 2
    maxItems: 3

  nvidia,host1x-class:
    description: |
      Host1x class of the engine, used to specify the targeted engine
      when programming the engine through Host1x channels or when
      configuring engine-specific behavior in Host1x.
    default: 0x21
    $ref: /schemas/types.yaml#/definitions/uint32

required:
  - compatible

Annotation

Immediate include surface: `dt-bindings/clock/tegra186-clock.h`, `dt-bindings/memory/tegra186-mc.h`, `dt-bindings/power/tegra186-powergate.h`, `dt-bindings/reset/tegra186-reset.h`.
Atlas domain: Support Tooling And Documentation / Documentation.
Implementation status: atlas-only.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.