Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml- Extension
.yaml- Size
- 4247 bytes
- Lines
- 152
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/interrupt-controller/irq.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-adc5-gen3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm's SPMI PMIC ADC5 Gen3
maintainers:
- Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
description: |
SPMI PMIC5 Gen3 voltage ADC (ADC) provides interface to clients to read
voltage. It is a 16-bit sigma-delta ADC. It also performs the same thermal
monitoring function as the existing ADC_TM devices.
The interface is implemented on SDAM (Shared Direct Access Memory) peripherals
on the master PMIC rather than a dedicated ADC peripheral. The number of PMIC
SDAM peripherals allocated for ADC is not correlated with the PMIC used, it is
programmed in FW (PBS) and is fixed per SOC, based on the SOC requirements.
All boards using a particular (SOC + master PMIC) combination will have the
same number of ADC SDAMs supported on that PMIC.
properties:
compatible:
const: qcom,spmi-adc5-gen3
reg:
items:
- description: SDAM0 base address in the SPMI PMIC register map
- description: SDAM1 base address
minItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 0
"#io-channel-cells":
const: 1
"#thermal-sensor-cells":
const: 1
interrupts:
items:
- description: SDAM0 end of conversion (EOC) interrupt
- description: SDAM1 EOC interrupt
minItems: 1
patternProperties:
"^channel@[0-9a-f]+$":
type: object
unevaluatedProperties: false
$ref: /schemas/iio/adc/qcom,spmi-vadc-common.yaml
description:
Represents the external channels which are connected to the ADC.
properties:
qcom,decimation:
enum: [ 85, 340, 1360 ]
default: 1360
qcom,hw-settle-time:
enum: [ 15, 100, 200, 300, 400, 500, 600, 700,
1000, 2000, 4000, 8000, 16000, 32000, 64000, 128000 ]
default: 15
qcom,avg-samples:
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/irq.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.