Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml
Extension
.yaml
Size
2781 bytes
Lines
105
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Generic i.MX bus frequency device

maintainers:
  - Peng Fan <peng.fan@nxp.com>

description: |
  The i.MX SoC family has multiple buses for which clock frequency (and
  sometimes voltage) can be adjusted.

  Some of those buses expose register areas mentioned in the memory maps as GPV
  ("Global Programmers View") but not all. Access to this area might be denied
  for normal (non-secure) world.

  The buses are based on externally licensed IPs such as ARM NIC-301 and
  Arteris FlexNOC but DT bindings are specific to the integration of these bus
  interconnect IPs into imx SOCs.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - fsl,imx8mm-nic
              - fsl,imx8mn-nic
              - fsl,imx8mp-nic
              - fsl,imx8mq-nic
          - const: fsl,imx8m-nic
      - items:
          - enum:
              - fsl,imx8mm-noc
              - fsl,imx8mn-noc
              - fsl,imx8mp-noc
              - fsl,imx8mq-noc
          - const: fsl,imx8m-noc
      - const: fsl,imx8m-nic

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  operating-points-v2: true
  opp-table:
    type: object

  fsl,ddrc:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to DDR Controller.

  '#interconnect-cells':
    description:
      If specified then also act as an interconnect provider. Should only be
      set once per soc on the main noc.
    const: 1

required:
  - compatible
  - clocks

additionalProperties: false

examples:

Annotation

Implementation Notes