Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml

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Linux kernel
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Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
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.yaml
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9048 bytes
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314
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Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
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atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Generic Interrupt Controller, version 3

maintainers:
  - Marc Zyngier <maz@kernel.org>

description: |
  AArch64 SMP cores are often associated with a GICv3, providing Private
  Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
  Software Generated Interrupts (SGI), and Locality-specific Peripheral
  Interrupts (LPI).

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - qcom,msm8996-gic-v3
          - const: arm,gic-v3
      - const: arm,gic-v3

  interrupt-controller: true

  "#address-cells":
    enum: [ 0, 1, 2 ]
  "#size-cells":
    enum: [ 1, 2 ]

  ranges: true

  "#interrupt-cells":
    description: |
      Specifies the number of cells needed to encode an interrupt source.
      Must be a single cell with a value of at least 3.
      If the system requires describing PPI affinity, then the value must
      be at least 4.

      The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
      interrupts, 2 for interrupts in the Extended SPI range, 3 for the
      Extended PPI range. Other values are reserved for future use.

      The 2nd cell contains the interrupt number for the interrupt type.
      SPI interrupts are in the range [0-987]. PPI interrupts are in the
      range [0-15]. Extended SPI interrupts are in the range [0-1023].
      Extended PPI interrupts are in the range [0-63].

      The 3rd cell is the flags, encoded as follows:
      bits[3:0] trigger type and level flags.
        1 = edge triggered
        4 = level triggered

      The 4th cell is a phandle to a node describing a set of CPUs this
      interrupt is affine to. The interrupt must be a PPI, and the node
      pointed must be a subnode of the "ppi-partitions" subnode. For
      interrupt types other than PPI or PPIs that are not partitioned,
      this cell must be zero. See the "ppi-partitions" node description
      below.

      Cells 5 and beyond are reserved for future use and must have a value
      of 0 if present.
    enum: [ 3, 4 ]

Annotation

Implementation Notes