Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml

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Linux kernel
Corpus path
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml
Extension
.yaml
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7011 bytes
Lines
268
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Generic Interrupt Controller, version 5

maintainers:
  - Lorenzo Pieralisi <lpieralisi@kernel.org>
  - Marc Zyngier <maz@kernel.org>

description: |
  The GICv5 architecture defines the guidelines to implement GICv5
  compliant interrupt controllers for AArch64 systems.

  The GICv5 specification can be found at
  https://developer.arm.com/documentation/aes0070

  The GICv5 architecture is composed of multiple components:
    - one or more IRS (Interrupt Routing Service)
    - zero or more ITS (Interrupt Translation Service)

  The architecture defines:
    - PE-Private Peripheral Interrupts (PPI)
    - Shared Peripheral Interrupts (SPI)
    - Logical Peripheral Interrupts (LPI)

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  compatible:
    const: arm,gic-v5

  "#address-cells":
    enum: [ 1, 2 ]

  "#size-cells":
    enum: [ 1, 2 ]

  ranges: true

  "#interrupt-cells":
    description: |
      The 1st cell corresponds to the INTID.Type field in the INTID; 1 for PPI,
      3 for SPI. LPI interrupts must not be described in the bindings since
      they are allocated dynamically by the software component managing them.

      The 2nd cell contains the interrupt INTID.ID field.

      The 3rd cell is the flags, encoded as follows:
      bits[3:0] trigger type and level flags.

        1 = low-to-high edge triggered
        2 = high-to-low edge triggered
        4 = active high level-sensitive
        8 = active low level-sensitive

    const: 3

  interrupt-controller: true

  interrupts:
    description:
      The VGIC maintenance interrupt.
    maxItems: 1

required:
  - compatible

Annotation

Implementation Notes