Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-interrupt.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-interrupt.yaml

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Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-interrupt.yaml
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Support Tooling And Documentation: configuration, schema, or hardware description
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-interrupt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ASPEED AST2700 Interrupt Controllers (INTC0/INTC1)

description: |
  The ASPEED AST2700 SoC integrates two interrupt controller designs:

    - INTC0: Primary controller that routes interrupt sources to upstream,
      processor-specific interrupt controllers

    - INTC1: Secondary controller whose interrupt outputs feed into INTC0

  The SoC contains four processors to which interrupts can be routed:

    - PSP: Primary Service Processor (Cortex-A35)
    - SSP: Secondary Service Processor (Cortex-M4)
    - TSP: Tertiary Service Processor (Cortex-M4)
    - BMCU: Boot MCU (a RISC-V microcontroller)

  The following diagram illustrates the overall architecture of the
  ASPEED AST2700 interrupt controllers:

                  +-----------+                +-----------+
                  |   INTC0   |                | INTC1(0)  |
                  +-----------+                +-----------+
                  |   Router  | +-----------+  |   Router  |
                  | out   int | +Peripheral +  | out   int |
  +-----------+   |  0     0  <-+Controllers+  | INTM      | +-----------+
  |PSP GIC  <-|---+  .     .  | +-----------+  |  .     .  <-+Peripheral +
  +-----------+   |  .     .  |                |  .     .  | +Controllers+
  +-----------+   |  .     .  |                |  .     .  | +-----------+
  |SSP NVIC <-|---+  .     .  <----------------+  .     .  |
  +-----------+   |  .     .  |                |  .     .  |
  +-----------+   |  .     .  <--------        |  .     .  |
  |TSP NVIC <-|---+  .     .  |       |    ----+  .     .  |
  +-----------+   |  .     .  |       |    |   |  O     P  |
                  |  .     .  |       |    |   +-----------+
                  |  .     .  <----   |    --------------------
                  |  .     .  |   |   |        +-----------+  |
                  |  M     N  |   |   ---------+  INTC1(1) |  |
                  +-----------+   |            +-----------+  |
                                  |                  .        |
                                  |            +-----------+  |
                                  -------------+  INTC1(N) |  |
                                               +-----------+  |
  +--------------+                                            |
  + BMCU APLIC <-+---------------------------------------------
  +--------------+

  INTC0 supports:
    - 128 local peripheral interrupt inputs
    - Fan-in from up to three INTC1 instances via banked interrupt lines (INTM)
    - Local peripheral interrupt outputs
    - Merged interrupt outputs
    - Software interrupt outputs (SWINT)
    - Configurable interrupt routes targeting the PSP, SSP, and TSP

  INTC1 supports:
    - 192 local peripheral interrupt inputs
    - Banked interrupt outputs (INTM, 5 x 6 banks x 32 interrupts per bank)
    - Configurable interrupt routes targeting the PSP, SSP, TSP, and BMCU

  One INTC1 instance is always present, on the SoC's IO die. A further two
  instances may be attached to the SoC's one INTC0 instance via LTPI (LVDS
  Tunneling Protocol & Interface).

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