Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml

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Linux kernel
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Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
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.yaml
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Support Tooling And Documentation
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Documentation
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Support Tooling And Documentation: configuration, schema, or hardware description
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM7120-style Level 2 and Broadcom BCM3380 Level 1 / Level 2

maintainers:
  - Florian Fainelli <f.fainelli@gmail.com>

description: >
  This interrupt controller hardware is a second level interrupt controller that
  is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
  platforms. It can be found on BCM7xxx products starting with BCM7120.

  Such an interrupt controller has the following hardware design:

  - outputs multiple interrupts signals towards its interrupt controller parent

  - controls how some of the interrupts will be flowing, whether they will
    directly output an interrupt signal towards the interrupt controller parent,
    or if they will output an interrupt signal at this 2nd level interrupt
    controller, in particular for UARTs

  - has one 32-bit enable word and one 32-bit status word

  - no atomic set/clear operations

  - not all bits within the interrupt controller actually map to an interrupt

  The typical hardware layout for this controller is represented below:

  2nd level interrupt line		Outputs for the parent controller (e.g: ARM GIC)

  0 -----[ MUX ] ------------|==========> GIC interrupt 75
            \-----------\
                         |
  1 -----[ MUX ] --------)---|==========> GIC interrupt 76
            \------------|
                         |
  2 -----[ MUX ] --------)---|==========> GIC interrupt 77
            \------------|
                         |
  3 ---------------------|
  4 ---------------------|
  5 ---------------------|
  7 ---------------------|---|===========> GIC interrupt 66
  9 ---------------------|
  10 --------------------|
  11 --------------------/

  6 ------------------------\
                            |===========> GIC interrupt 64
  8 ------------------------/

  12 ........................ X
  13 ........................ X           (not connected)
  ..
  31 ........................ X

  The BCM3380 Level 1 / Level 2 interrupt controller shows up in various forms
  on many BCM338x/BCM63xx chipsets. It has the following properties:

  - outputs a single interrupt signal to its interrupt controller parent

  - contains one or more enable/status word pairs, which often appear at
    different offsets in different blocks

  - no atomic set/clear operations

Annotation

Implementation Notes