Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml- Extension
.yaml- Size
- 11594 bytes
- Lines
- 319
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/clock/imx8-lpcg.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/fsl,imx8qxp-dc-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller interrupt controller
description: |
The Display Controller has a built-in interrupt controller with the following
features for all relevant HW events:
* Enable bit (mask)
* Status bit (set by an HW event)
* Preset bit (can be used by SW to set status)
* Clear bit (used by SW to reset the status)
Each interrupt can be connected as IRQ (maskable) and/or NMI (non-maskable).
Alternatively the un-masked trigger signals for all HW events are provided,
allowing it to use a global interrupt controller instead.
Each interrupt can be protected against SW running in user mode. In that case,
only privileged AHB access can control the interrupt status.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-intc
reg:
maxItems: 1
clocks:
maxItems: 1
interrupt-controller: true
"#interrupt-cells":
const: 1
interrupts:
items:
- description: store9 shadow load interrupt(blit engine)
- description: store9 frame complete interrupt(blit engine)
- description: store9 sequence complete interrupt(blit engine)
- description:
extdst0 shadow load interrupt
(display controller, content stream 0)
- description:
extdst0 frame complete interrupt
(display controller, content stream 0)
- description:
extdst0 sequence complete interrupt
(display controller, content stream 0)
- description:
extdst4 shadow load interrupt
(display controller, safety stream 0)
- description:
extdst4 frame complete interrupt
(display controller, safety stream 0)
- description:
extdst4 sequence complete interrupt
(display controller, safety stream 0)
- description:
extdst1 shadow load interrupt
(display controller, content stream 1)
- description:
extdst1 frame complete interrupt
Annotation
- Immediate include surface: `dt-bindings/clock/imx8-lpcg.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.