Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml- Extension
.yaml- Size
- 1627 bytes
- Lines
- 61
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC)
maintainers:
- Rahul Tanwar <rtanwar@maxlinear.com>
description: |
Intel's Advanced Programmable Interrupt Controller (APIC) is a
family of interrupt controllers. The APIC is a split
architecture design, with a local component (LAPIC) integrated
into the processor itself and an external I/O APIC. Local APIC
(lapic) receives interrupts from the processor's interrupt pins,
from internal sources and from an external I/O APIC (ioapic).
And it sends these to the processor core for handling.
See [1] Chapter 8 for more details.
Many of the Intel's generic devices like hpet, ioapic, lapic have
the ce4100 name in their compatible property names because they
first appeared in CE4100 SoC.
This schema defines bindings for I/O APIC interrupt controller.
[1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf
properties:
compatible:
const: intel,ce4100-ioapic
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
additionalProperties: false
examples:
- |
ioapic1: interrupt-controller@fec00000 {
compatible = "intel,ce4100-ioapic";
reg = <0xfec00000 0x1000>;
interrupt-controller;
#interrupt-cells = <2>;
};
Annotation
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.