Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml- Extension
.yaml- Size
- 2907 bytes
- Lines
- 128
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Loongson Local I/O Interrupt Controller
maintainers:
- Jiaxun Yang <jiaxun.yang@flygoat.com>
description: |
This interrupt controller is found in the Loongson-3 family of chips and
Loongson-2K series chips, as the primary package interrupt controller which
can route local I/O interrupt to interrupt lines of cores.
Be aware of the following points.
1.The Loongson-2K0500 is a single core CPU;
2.The Loongson-2K0500/2K1000 has 64 device interrupt sources as inputs, so we
need to define two nodes in dts{i} to describe the "0-31" and "32-61" interrupt
sources respectively.
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
enum:
- loongson,liointc-1.0
- loongson,liointc-1.0a
- loongson,liointc-2.0
reg:
minItems: 1
maxItems: 3
reg-names:
items:
- const: main
- const: isr0
- const: isr1
minItems: 2
'#address-cells':
const: 0
interrupt-controller: true
interrupts:
description:
Interrupt source of the CPU interrupts.
minItems: 1
maxItems: 4
interrupt-names:
description: List of names for the parent interrupts.
items:
pattern: int[0-3]
minItems: 1
maxItems: 4
'#interrupt-cells':
const: 2
loongson,parent_int_map:
description: |
This property points how the children interrupts will be mapped into CPU
interrupt lines. Each cell refers to a parent interrupt line from 0 to 3
and each bit in the cell refers to a child interrupt from 0 to 31.
If a CPU interrupt line didn't connect with liointc, then keep its
cell with zero.
Annotation
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.